1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to a bipolar-transistor type semiconductor memory device having a diode-matrix type decoder and a redundancy circuit portion for replacing a defective circuit portion such as a defective memory cell.
2. Description of the Related Art
In a random-access memory (RAM) device, a large number of memory cells are arranged along rows and columns. The density of defects generated in such a semiconductor memory device during the manufacture thereof is relatively independent of the integration density of the device. Rather, the defects are a result of semiconductor manufacturing technology. In general, the higher the integration density of the device, the greater the ratio of normal memory cells to defective memory cells. This is one of the advantages of increasing the integration density of a semiconductor memory device. Even if a device includes only one defective memory cell, however, the device cannot be operated normally and, therefore, must be scrapped. As a result, despite the lower ratio of defective memory cells, greater integration density means reduced manufacturing yield.
In a metal-insulator-semiconductor (MIS) type RAM, in order to overcome the problem of defective memory cells, use is made of redundancy memory cells. When a defective memory cell is detected, a redundancy memory cell row or column is selected instead of the memory cell row or column including the defective memory cell. In general, one or two redundancy memory cell rows or columns are usually provided.
With improvements in integration technology for bipolar-transistor type RAMs and the requirement of larger numbers of memory cells, however, bipolar-transistor type RAM devices having a large number of memory cells have come into demand, and accordingly, this has led to a demand for bipolar-transistor type RAMs having a redundancy configuration.
Generally, in the bipolar-transistor type memory device, two kinds of memory devices are well known, i.e., one which includes a logic type decoder, and another which includes a diode matrix type decoder. Generally, the memory device including the logic type decoder has an advantage in that the response time is rapid, and as a result, the switching from a predetermined operation to a next operation is smoothly performed. However, a memory device including the above logic type decoder has a drawback in that it is necessary to provide a large number of constant current sources, especially when the capacity of the memory device is large (for example, when the capacity of the memory device is 64 kilo bits, it is necessary to provide two hundred and fifty six constant current sources, each of which is provided in a word driver unit), and thus, the power consumption increases in accordance with the increase of the number of the constant current sources. In other words, the logic type decoder is not suitable for a memory device having a large capacity.
On the other hand, the memory device having the diode matrix type decoder has an advantage in that it is possible to raise the efficiency of the current by decreasing the number of constant current sources, and thus, decrease the power consumption. In other words, the diode matrix type decoder is more suitable for a memory device having a large capacity.
Although it has been proposed to provide a redundancy configuration in a memory device including a logic type decoder, a memory device having a redundancy configuration and a diode matrix type decoder has not been provided as yet.